Integrated Circuits (ICs) > Memory > FIFO > Texas-Instruments-SN74ACT3651-20PQ

Texas Instruments SN74ACT3651-20PQ

Texas Instruments

Part Number:	Texas Instruments SN74ACT3651-20PQ
Manufacturer:	Texas Instruments
Part Type:	Integrated Circuits (ICs) > Memory > FIFO > Texas-Instruments-SN74ACT3651-20PQ
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Description:	Bi-Directional FIFO, 2KX36, 13ns, Synchronous, CMOS, PQFP132

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Bi-Directional FIFO, 2KX36, 13ns, Synchronous, CMOS, PQFP132

Specifications

TYPE	DESCRIPTION
Case/Package	PQFP
Mount	Surface Mount
Number of Pins	132
Weight	4.608697 g
Access Time	13 ns
Bus Directional	Bidirectional
Data Bus Width	36 b
Density	72 kb
Direction	Bidirectional
Element Configuration	Dual
Frequency	50 MHz
FWFT Support	No
Max Frequency	50 MHz
Max Operating Temperature	70 °C
Max Supply Current	400 µA
Max Supply Voltage	5.5 V
Memory Size	9 kB
Min Operating Temperature	0 °C
Min Supply Voltage	4.5 V
Number of Circuits	2
Operating Supply Voltage	5 V
Packaging	Bulk
Programmable Flags Support	Yes
Retransmit Capability	Yes

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Datasheet

View & Download Texas-Instruments-SN74ACT3651-20PQ Datasheet

Alternate Descriptions

Descriptions of Texas Instruments SN74ACT3651-20PQ provided by its distributors.
Bi-Directional FIFO, 2KX36, 13ns, Synchronous, CMOS, PQFP132
FIFO Mem Sync Dual Depth Bi-Dir 2K x 36 132-Pin BQFP Tray
FIFO Logic IC; FIFO Function:Synchronous; Access Time, Tacc:13ns; Frequency:50MHz; Memory Organization - FIFO:2048 x 36bit; Supply Voltage Range:4.5V to 5.5V; Logic Case Style:BQFP; No. of Pins:132 ;RoHS Compliant: Yes
The SN74ACT3651 is a high-speed, low-power, CMOS clocked FIFO memory that supports clock frequencies up to 67 MHz and has read access times as fast as 11 ns. The 2048 36 dual-port SRAM FIFO buffers data from port A to port B. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port takes place with two 36-bit mailbox registers. Each mailbox register has a flag that signals when new mail has been stored. Two or more devices are used in parallel to create wider data paths. Expansion is also possible in word depth. The SN74ACT3651 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous control. The input-ready (IR) flag and almost-full (AF\) flag of the FIFO are two-stage synchronized to CLKA. The output-ready (OR) flag and almost-empty (AE\) flag of the FIFO are two-stage synchronized to CLKB. Offset values for AF\ and AE\ are programmed from port A or through a serial input. The SN74ACT3651 is characterized for operation from 0C to 70C. For more information on this device family, see the following application reports: FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering (literature number SCAA009) FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number SCAA007) Metastability Performance of Clocked FIFOs (literature number SCZA004)

Texas Instruments SN74ACT3651-20PQ

Texas Instruments

Specifications

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