Integrated Circuits (ICs) > Logic ICs > Latches and Flip Flops > SN74F112N
SN74F112N
| Part Number: | SN74F112N |
| Manufacturer: | Texas Instruments |
| Part Type: | Integrated Circuits (ICs) > Logic ICs > Latches and Flip Flops > SN74F112N |
| Qty Available: | |
| Description: | Dual J-K Negative-Edge-Triggered Flip-Flop With Clear And Preset 16-PDIP 0 to 70 |
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Dual J-K Negative-Edge-Triggered Flip-Flop With Clear And Preset 16-PDIP 0 to 70
Specifications
| TYPE | DESCRIPTION |
| Case/Package | PDIP |
| Mount | Through Hole |
| Number of Pins | 16 |
| Weight | 951.693491 mg |
| Clock Edge Trigger Type | Negative Edge |
| Frequency | 100 MHz |
| High Level Output Current | -1 mA |
| Logic Function | AND, Flip-Flop, JK-Type |
| Low Level Output Current | 20 mA |
| Max Operating Temperature | 70 °C |
| Max Supply Voltage | 5.5 V |
| Min Operating Temperature | 0 °C |
| Min Supply Voltage | 4.5 V |
| Number of Bits | 2 |
| Number of Bits per Element | 1 |
| Number of Circuits | 2 |
| Number of Elements | 2 |
| Number of Input Lines | 2 |
| Number of Output Lines | 1 |
| Operating Supply Voltage | 5 V |
| Output Current | 20 mA |
| Output Type | TTL |
| Polarity | Non-Inverting |
| Propagation Delay | 4.6 ns |
| Turn-On Delay Time | 4.6 ns |
| Height | 5.08 mm |
| Length | 19.3 mm |
| Thickness | 3.9 mm |
| Width | 6.35 mm |
Images
Documentation for Texas Instruments SN74F112N
| Datasheet | View & Download SN74F112N Datasheet |
| Technical Drawing | View & Download SN74F112N Technical Drawing |
| Datasheet | View & Download SN74F112N Datasheet |
| Datasheet | View & Download SN74F112N Datasheet |
| Datasheet | View & Download SN74F112N Datasheet |
| Datasheet | View & Download SN74F112N Datasheet |
| Datasheet | View & Download SN74F112N Datasheet |
| Datasheet | View & Download SN74F112N Datasheet |
| Datasheet | View & Download SN74F112N Datasheet |
| Datasheet | View & Download SN74F112N Datasheet |
Alternate Descriptions
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