Integrated Circuits (ICs) > Memory > FIFO > SN74ALS232BFN

SN74ALS232BFN

Texas Instruments

Part Number:	SN74ALS232BFN
Manufacturer:	Texas Instruments
Part Type:	Integrated Circuits (ICs) > Memory > FIFO > SN74ALS232BFN
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Description:	FIFO Mem Async Dual Uni-Dir 16 x 4 20-Pin PLCC Tube

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FIFO Mem Async Dual Uni-Dir 16 x 4 20-Pin PLCC Tube

Specifications

TYPE	DESCRIPTION
Case/Package	PLCC
Mount	Surface Mount
Number of Pins	20
Data Rate	40 Mbps
Frequency	40 MHz
Max Operating Temperature	70 °C
Min Operating Temperature	0 °C
Case/Package	PLCC
Mount	Surface Mount
Number of Pins	20
Data Rate	40 Mbps
Frequency	40 MHz
Max Operating Temperature	70 °C
Min Operating Temperature	0 °C

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Documentation for Texas Instruments SN74ALS232BFN

Datasheet	View & Download SN74ALS232BFN Datasheet
Datasheet	View & Download SN74ALS232BFN Datasheet
Datasheet	View & Download SN74ALS232BFN Datasheet
Datasheet	View & Download SN74ALS232BFN Datasheet

Alternate Descriptions

Descriptions of Texas Instruments SN74ALS232BFN provided by its distributors.
FIFO Mem Async Dual Uni-Dir 16 x 4 20-Pin PLCC Tube
FIFO Logic IC; Logic Family:ALS; Frequency Max:50MHz; Supply Voltage Min:4.5V; Supply Voltage Max:5.5V; Package/Case:20-PLCC; No. of Pins:20; Operating Temperature Range:0°C to +70°C; Leaded Process Compatible:No ;RoHS Compliant: No
This 64-bit memory features high speed and fast fall-through times. It is organized as 16 words by 4 bits. A first-in, first-out (FIFO) memory is a storage device that allows data to be written into and read from its array at independent data rates. This FIFO is designed to process data at rates up to 40MHz in a bit-parallel format, word by word. Data is written into memory on a low-to-high transition at the load-clock (LDCK) input and is read out on a low-to-high transition at the unload-clock (UNCK) input. The memory is full when the number of words clocked in exceeds by 16 the number of words clocked out. When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory is empty, UNCK signals have no effect. Status of the FIFO memory is monitored by the FULL\ and EMPTY\ output flags. The FULL\ output is low when the memory is full and high when it is not full. The EMPTY\ output is low when the memory is empty and high when it is not empty. A low level on the reset (RST\) input resets the internal stack-control pointers and also sets EMPTY\ low and sets FULL\ high. The Q outputs are not reset to any specific logic level. The first low-to-high transition on LDCK, after either a RST\ pulse or from an empty condition, causes EMPTY\ to go high and the data to appear on the Q outputs. It is important to note that the first word does not have to be unloaded. Data outputs are noninverting with respect to the data inputs and are at high impedance when the output-enable (OE) input is low. OE does not affect the FULL\ or EMPTY\ output flags. Cascading is easily accomplished in the word-width direction but is not possible in the word-depth direction. The SN74ALS232B is characterized for operation from 0C to 70C.
Descriptions of Texas Instruments SN74ALS232BFN provided by its distributors.
FIFO Mem Async Dual Uni-Dir 16 x 4 20-Pin PLCC Tube
FIFO Logic IC; Logic Family:ALS; Frequency Max:50MHz; Supply Voltage Min:4.5V; Supply Voltage Max:5.5V; Package/Case:20-PLCC; No. of Pins:20; Operating Temperature Range:0°C to +70°C; Leaded Process Compatible:No ;RoHS Compliant: No
This 64-bit memory features high speed and fast fall-through times. It is organized as 16 words by 4 bits. A first-in, first-out (FIFO) memory is a storage device that allows data to be written into and read from its array at independent data rates. This FIFO is designed to process data at rates up to 40MHz in a bit-parallel format, word by word. Data is written into memory on a low-to-high transition at the load-clock (LDCK) input and is read out on a low-to-high transition at the unload-clock (UNCK) input. The memory is full when the number of words clocked in exceeds by 16 the number of words clocked out. When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory is empty, UNCK signals have no effect. Status of the FIFO memory is monitored by the FULL\ and EMPTY\ output flags. The FULL\ output is low when the memory is full and high when it is not full. The EMPTY\ output is low when the memory is empty and high when it is not empty. A low level on the reset (RST\) input resets the internal stack-control pointers and also sets EMPTY\ low and sets FULL\ high. The Q outputs are not reset to any specific logic level. The first low-to-high transition on LDCK, after either a RST\ pulse or from an empty condition, causes EMPTY\ to go high and the data to appear on the Q outputs. It is important to note that the first word does not have to be unloaded. Data outputs are noninverting with respect to the data inputs and are at high impedance when the output-enable (OE) input is low. OE does not affect the FULL\ or EMPTY\ output flags. Cascading is easily accomplished in the word-width direction but is not possible in the word-depth direction. The SN74ALS232B is characterized for operation from 0C to 70C.

SN74ALS232BFN

Texas Instruments

Specifications

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Documentation for Texas Instruments SN74ALS232BFN

Alternate Descriptions

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