Integrated Circuits (ICs) > Memory > FIFO > SN74ACT3631-30PQ

SN74ACT3631-30PQ

Texas Instruments

Part Number:	SN74ACT3631-30PQ
Manufacturer:	Texas Instruments
Part Type:	Integrated Circuits (ICs) > Memory > FIFO > SN74ACT3631-30PQ
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Description:	FIFO Mem Sync Dual Depth Bi-Dir 512 x 36 132-Pin BQFP Tray

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FIFO Mem Sync Dual Depth Bi-Dir 512 x 36 132-Pin BQFP Tray

Specifications

TYPE	DESCRIPTION
Case/Package	PQFP
Mount	Surface Mount
Number of Pins	132
Weight	4.608697 g
Access Time	15 ns
Bus Directional	Bidirectional
Data Bus Width	36 b
Density	18 kb
Direction	Bidirectional
Element Configuration	Dual
Frequency	33.4 MHz
FWFT Support	No
Max Frequency	33.4 MHz
Max Operating Temperature	70 °C
Max Supply Current	400 µA
Max Supply Voltage	5.5 V
Memory Size	2.3 kB
Min Operating Temperature	0 °C
Min Supply Voltage	4.5 V
Number of Circuits	2
Operating Supply Voltage	5 V
Packaging	Bulk
Programmable Flags Support	Yes
Retransmit Capability	Yes

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Alternate Descriptions

Descriptions of Texas Instruments SN74ACT3631-30PQ provided by its distributors.
FIFO Mem Sync Dual Depth Bi-Dir 512 x 36 132-Pin BQFP Tray
FIFO, 512X36, 15ns, Synchronous, CMOS, PQFP132
IC CLK DUAL FIFO MEMORY 132-QFP
IC SDRAM 512MBIT 533MHZ 84FBGA
The SN74ACT3631 is a high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 11 ns. The 512 36 dual-port SRAM FIFO buffers data from port A to port B. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port can take place with two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can be used in parallel to create wider datapaths. Expansion also is possible in word depth. The SN74ACT3631 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous control. The input-ready (IR) flag and almost-full (AF\) flag of the FIFO are two-stage synchronized to CLKA. The output-ready (OR) flag and almost-empty (AE\) flag of the FIFO are two-stage synchronized to CLKB. Offset values for the AF and AE flags of the FIFO can be programmed from port A or through a serial input. The SN74ACT3631 is characterized for operation from 0C to 70C. For more information on this device family, see the following application reports: FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering (literature number SCAA007) FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number SCAA007) Metastability Performance of Clocked FIFOs (literature number SCZA004).

SN74ACT3631-30PQ

Texas Instruments

Specifications

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